For very high-speed serial data transmission typically embedded clock signaling is applied; the transmitter utilizes a certain encoding scheme to include sufficient clock information in the serialized data stream to allow the receiving side to retrieve the originally transmitted data by means of Clock and Data Recovery (CDR) and a complementary decoder.
Coding schemes may additionally provide signal conditioning like dc-balancing and/or spectral shaping. An often applied coding scheme is 8B10B, where every data byte translates into a 10-bit symbol, and that also provides control symbols, some of them including unique sequences to unambiguously determine the symbol boundaries.
The Clock and Data Recovery (CDR) function in the receiving path can be accomplished by a synchronous solution utilizing a data-tracking phase-locked loop (PLL) that is feedback-controlled to sample the center of the bits, or by an over-sampled solution which samples the input signal more than twice per bit period with a clock derived from a reference clock while the samples are processed by a digital data & clock recovery algorithm to recover the original data.
Synchronous solutions have some advantages compared to over-sampled solution, including that they recover a synchronous analog clock which can for example be used for re-transmission or for synchronous data post-processing, they typically consume less power, and they support higher data rates when implemented in a given process technology.
Disadvantages of synchronous solutions are their start-up complications, including start-up time, frequency capture range, and sensitivity to false-lock.
Data-tracking PLLs typically do not have intrinsic frequency detection capabilities, and will therefore not lock correctly without additional frequency acquisitions aids. Frequently used early-late or bang-bang data-tracking PLLs have a limited frequency capture range around the momentary free-running oscillator frequency. The frequency may drift away and/or false-lock may occur if the data rate is outside that range. This means that the oscillator frequency has to be brought close enough to the data frequency by means of additional functionality to guarantee robust operation.
A conventional solution is to add a clock-multiplier PLL loop next to the data-tracking loop in the CDR as illustrated in FIG. 1. Using a sufficiently accurate reference clock and a phase-frequency detector (PFD), the oscillator frequency is adapted to become close to the data rate, such that the data rate will be within the frequency capture range of the CDR when switching to data-tracking mode. However, this typically requires a rather accurate reference clock, which can be a major penalty if such a clock is not already present in the application for other reasons. Furthermore, special care must be taken that no significant frequency steps occur due to the switching to data-tracking mode, as otherwise the data rate may be located outside the CDR frequency capture range again.
Alternatively, a toggling training pattern can be applied to the input of the receiver for synchronization purposes. Because a data-tracking PLL typically does not have intrinsic frequency detection capabilities, usually a second loop with a phase-frequency-detector (PFD) is added, utilizing the toggling input data pattern as a reference clock signal during training, as illustrated in FIG. 2. A disadvantage of that solution is that the input signal needs to drive additional circuitry, which degrades performance due to extra parasitic loading. Furthermore, the input signal will typically be low-swing differential and is therefore most likely not capable of directly driving a logic divider or PFD. Therefore an additional amplifying buffer would be required, which needs to have a high bandwidth if the training pattern is an alternating bit sequence at the bit rate. Special care must be taken in this case too that no significant frequency steps occur due to the switching to data-tracking mode, as otherwise the data rate may become located outside the CDR frequency capture range again.